1. Field of the Invention
The present invention generally relates to an access control device for a bus bridge circuit, which are capable of accurately performing access control from a first bus to a second bus.
This application relies for priority on Japanese patent application, Serial Number 28456/2002, filed Feb. 5, 2002, which is incorporated herein by reference in its entirety.
2. Description of the Related Art
Electronic equipment or devices such as a cellular phone, an electronic notebook, car navigation equipment, etc. have been advanced in recent years. There has been an increasingly demand for a semiconductor chip equipped with an application-specific integrated circuit (ASIC) associated with the functions of these electronic equipment. Such a semiconductor chip builds therein a CPU and its associated circuits as core parts and includes parts other than those, which comprise a gate array and the like. The semiconductor chip is capable of making circuit design for respective applications. As a suitable example of this type of semiconductor chip, there is known, for example, an AMBA (Advanced Microcontroller Bus Architecture) manufactured by ARM Ltd. AMBA specifications are used to define the on-chip communication protocol or standard for designing high-performance 32-bit and 16-bit embedded microcontrollers refer to Japanese Laid Open Patent Application No. 2000-112878, for example).
FIG. 1 is a diagram for describing the present invention. Since, however, the prior art is also substantially identical to the present invention in overall configuration, the prior art will be explained with reference to the present drawing. In FIG. 1, a system bus 1 is used in a high-performance system module, and a peripheral bus 2 is used in low-power peripheral devices. Abus bridge circuit 3 performs protocol conversion between the system bus 1 and the peripheral bus 2. This is because since the width of the peripheral bus 2 is narrower than that of the system bus 1, both are different in bus protocol from each other. When a CPU 11 obtains data write or read access to a first peripheral device 21 in FIG. 1 by way of example, it is necessary to carry out protocol conversion from a system bus protocol to a peripheral bus protocol.
In the AMBA specifications, a dedicated module for performing such protocol conversion has been prepared. In the module, a decoder 14 decodes an AHB (Advanced High performance Bus) address signal for the system bus 1 to thereby generate a select signal and an internal error signal for each of respective peripheral devices 21, 22, . . . , 20 placed under an APB (Advanced Peripheral Bus). Further, an internal signal is generated which indicates that each address is placed within a predetermined area and access is made to the predetermined peripheral device 21, 22, . . . or 20. An APB address equivalent to its corresponding address within the predetermined peripheral device is generated from an AHB address. Thus, when one attempts to manufacture each electronic equipment through the use of the above-described semiconductor chip, it is advantageous to comply with the above AMBA specifications.
On the other hand, the CPU 11 and the peripheral device 21 or the like have made use of clocks identical in cycle or period upon access to the peripheral device 21 or the like from the CPU 11 using the bus protocol conversion module based on the AMBA specifications. A period for the access was fixed to two cycles of the clock. Therefore, there was a case in which the operation of the peripheral device 21 or the like was slow and uncompleted within the fixed access period, and no access was finished. On the other hand, there is also known a method of lowering the frequency of a clock to enable such access according to the AMBA specifications. According to the method, however, the capability of each high-performance device connected to the system bus 1 for the CPU 11 and the like came to naught without making use of the capability thereof.